spice device model SUM110N03-04P vishay siliconix this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. document number: 72423 www.vishay.com 09-jun-04 1 n-channel 30-v (d-s) 175c mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0 to 10v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback c apacitance network is used to model the gate charge characteri stics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
spice device model SUM110N03-04P vishay siliconix www.vishay.com document number: 72423 2 09-jun-04 specifications (t j = 25 c unless otherwise noted) parameter symbol test conditions simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.8 v on-state drain current a i d(on) v ds = 5 v, v gs = 10 v 1375 a v gs = 10 v, i d = 20 a 0.0033 0.0033 v gs = 10 v, i d = 20 a, t j = 125c 0.0049 drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 20 a, t j = 175c 0.0058 ? v gs = 4.5 v, i d = 20 a 0.0052 0.0052 forward transconductance a g fs v ds = 15 v, i d = 20 a 70 s forward voltage a v sd i s = 100 a, v gs = 0 v 0.92 1.2 v dynamic b input capacitance c iss 5194 5100 output capacitance c oss 780 860 reverse transfe r capacitance c rss v gs = 0 v, v ds = 25 v, f = 1 mhz 292 430 pf total gate charge c q g 43 40 gate-source charge c q gs 18 18 gate-drain charge c q gd v ds = 15 v, v gs = 4.5 v, i d = 50 a 16 16 nc turn-on delay time c t d(on) 13 12 rise time c t r 15 12 turn-off delay time c t d(off) 31 40 fall time c t f v dd = 15 v, r l = 0.30 ? i d ? 50 a, v gen = 10 v, r g = 2.5 ? 31 10 ns notes a. pulse test; pulse width 300 s, duty cycle 2%. b. guaranteed by design, not s ubject to production testing. c. independent of operating temperature.
spice device model SUM110N03-04P vishay siliconix document number: 72423 www.vishay.com 09-jun-04 3 comparison of model with measured data (t j =25 c unless otherwise noted)
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